1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods for removing selected fins that are formed for FinFET semiconductor devices.
2. Description of the Related Art
FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device “A” that is formed above a semiconductor substrate B that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device A includes three illustrative fins C, a gate structure D, sidewall spacers E and a gate cap layer F. Trenches T are formed in the substrate B to define the fins C. The gate structure D is typically comprised of a layer of gate insulating material (not separately shown), e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device A. The fins C have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device A when it is operational. The portions of the fins C covered by the gate structure D are the channel regions of the FinFET device A. The FinFET device may have either a tri-gate or a dual gate channel structure. In a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Accordingly, for a given plot space (or footprint), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices.
A shallow trench isolation structure (not shown) is formed in the semiconducting substrate around the FinFET device so as to electrically isolate the FinFET device. Traditionally, isolation structures were always the first structures that were formed when manufacturing semiconductor devices. The isolation structures were formed by etching the trenches for the isolation structures and thereafter filling the trenches with the desired insulating material, e.g., silicon dioxide. Thereafter, the isolation structures were masked and trenches were etched into the substrate so as to define the fins. However, as the dimensions of the fins became smaller, problems arose with manufacturing the isolation structures before the fins were formed. As one example, trying to accurately define very small fins in regions that were separated by relatively large isolation regions was difficult due to the non-uniform spacing between various structures on the substrate. One manufacturing technique that is employed in manufacturing FinFET devices is to initially form the trenches T in the substrate B to define multiple “fins” that extend across the substrate, and thereafter remove some of the fins C where larger isolation structures will be formed. Using this type of manufacturing approach, better accuracy and repeatability may be achieved in forming the fins C to very small dimensions due to the more uniform environment in which the etching process that forms the trenches T is performed.
After the trenches T have been formed, some of the fins C must be removed to create room for or define the spaces where isolation regions will ultimately be formed. There are two commonly employed techniques for accomplishing the goal of removing the desired number of fins C. One such removal process is typically referred to as “Fins-cut-First,” as will be described with reference to FIGS. 1B-1E. Accordingly, FIG. 1B depicts the device 10 after a patterned hard mask layer 14, e.g., a patterned layer of silicon nitride, was formed above the substrate 12 in accordance with the desired fin pattern and pitch. In the depicted example, only a single fin will be removed, i.e., the fin 15 corresponding to the feature 14A, to make room for the isolation region. However, as will be recognized by those skilled in the art, depending upon the desired final size of the isolation region, more than one fin may be removed.
FIG. 1C depicts the device 10 after a patterned masking layer 16, e.g., a patterned layer of photoresist, has been formed above the patterned hard mask layer 14. The patterned masking layer 16 has an opening that exposes the feature 14A for removal.
FIG. 1D depicts the device 10 after an etching process has been performed through the patterned masking layer 16 so as to remove the exposed feature 14A of the patterned hard mask layer 14.
FIG. 1E depicts the device 10 after the patterned masking layer 16 was removed and after an etching process was performed through the patterned hard mask layer 14 (without the feature 14A) so as to define full-depth trenches 17 in the substrate 12 that define the fins 15. Due to the removal of the feature 14A, this etching process removes the portions of the substrate 12 that would have otherwise formed a fin 15 in the area under the feature 14A. One problem with the “fin-cut-first” approach is that it inevitably causes different fin sizes, i.e., the dimensions 15X and 15Y are different. This is especially true between fins 15 inside an array of fins and the fins at the edge of the active region that is close to the isolation region. This occurs due to etch loading effects wherein there are different etch rates and etch profiles due to differing patterning densities, pitch, etc.
FIG. 1F depicts the device 10 after several process operations were performed. First, a layer of insulating material 18, such as silicon dioxide, was formed so as to overfill the trenches 17. A chemical mechanical polishing (CMP) process was then performed to planarize the upper surface of the insulating material 18 with the top of the patterned hard mask 14. Thereafter, an etch-back process was performed to recess the layer of insulating material 18 between the fins 15 and thereby expose the upper portions of the fins 15, which corresponds to the final fin height of the fins 15. At this point in the process, the patterned hard mask 14 may or may not be thereafter removed. Next, the gate structure of the device 10 may be formed using either gate-first or gate-last manufacturing techniques.
Another fin removal process is typically referred to as “Fins-cut-Last,” as will be described with reference to FIGS. 1G-1J. FIG. 1G depicts the device 10 after the patterned hard mask layer 14 was formed above the substrate 12 in accordance with the desired fin pattern and pitch. As before, in the depicted example, only a single fin will be removed, i.e., the fin 15 corresponding to the feature 14A to make room for the isolation region. However, as will be recognized by those skilled in the art, depending upon the desired final size of the isolation region, more than one fin may be removed.
FIG. 1H depicts the device 10 after an etching process was performed through the patterned hard mask layer 14 so as to define full-depth trenches 17 in the substrate 12 that define the fins 15. Note that, in the Fins-cut-Last approach, the size of the fins is very uniform, i.e., the dimension 15A is approximately equal to the dimension 15B. This is primarily due to the fact that, in this approach, fins 15 are formed everywhere on the wafer and there is no undesirable etch loading effects.
FIG. 1I depicts the device 10 after several process operations were performed. First, a layer of insulating material 19, such as silicon dioxide, was formed so as to overfill the trenches 17. Then a CMP process was performed to planarize the upper surface of the layer of insulating material 19 with the patterned hard mask layer 14. Next, a patterned masking layer 22, e.g., a patterned layer of photoresist, was formed above the layer of insulating material 19. The patterned hard mask layer 22 has an opening that exposes the underlying fin for removal.
FIG. 1J depicts the device 10 after one or more etching processes were performed to remove the exposed portions of the layer of insulating material 19, the exposed portions of the hard mask layer 14, i.e., the feature 14A, and the underlying fin 15 by forming a trench 24 in the substrate 12. Inevitably, there will be some tapering of the sidewalls of the trench 24. Although not depicted in the drawings, after the trench 24 is formed, the patterned masking layer 22 will be removed and additional oxide material (not shown) will be formed through the opening 24A in the trench 24 where the fin 15 was removed. Then a chemical mechanical polishing (CMP) process will be performed to planarize the upper surface of all of the insulating materials with the top of the patterned hard mask 14. Thereafter, the isolation regions between devices will be masked and an etch-back process will be performed to recess the layer of insulating material 19 between the fins 15 for each device and thereby expose the upper portions of the fins 15, which corresponds to the final fin height of the fins 15.
One problem with the fins-cut-last approach is that if the size (CD) of the opening 24A of the trench 24 is relatively large, then there is less margin for misalignment error when removing the unwanted fin, i.e., there is less margin for error so as to avoid damage to the adjacent fins when the trench 24 is etched. Additionally, although not depicted, if the size of the opening 24A is kept small, there will typically be some residual portion of the fin 15 remaining at the bottom of the trench 24. Conversely, if the size of the opening 24A is increased in an effort to insure complete removal of the unwanted fin at the bottom of the trench 24, then there is a much greater likelihood of damaging the fins adjacent the trench 24 when it is etched. These issues only get worse as the depth of the trench 24 increases. Moreover, in many applications, e.g., SRAMs, it is often the case where only a single fin will need to be removed from the array or group of fins as initially formed. Removing a single fin without damaging adjacent fins is very difficult for at least the reasons noted above.
The present disclosure is directed to various methods of forming fins for FinFET semiconductor devices and the selective removal of some of the fins that may solve or reduce one or more of the problems identified above.